Static random access memory (SRAM) tends to have aggressive design rules to reduce the size of devices and increase the capacity in the system on chip (SoC) solutions, and therefore subject to more process variations. Device variations worsen as voltage decreases because there is less headroom at lower voltages.
The cell current of a weak bit can affect and degrade the performance of SRAM. A weak bit is a memory cell that has a relatively low current capacity as compared to a normal bit due to process/device variations. The weak bit results in a slow response time and affects the performance of SRAM. In particular, a weak bit affects the speed and the minimum power supply voltage of a single ended SRAM design. For example, a weak bit's cell current can have more than 30% lower current capacity compared to a normal bit due to process/device variations, and the speed can also degrade more than 30%.
Accordingly, new methods are desired to solve the above problems.